For the given circuit, the input digital signals are applied at the terminals A, B and C. What would be the output at the terminal y ?

The correct answer is the waveform representing a constant voltage of 5 V.

Step-by-step Analysis:

1. Logic Circuit Equations:
From the given circuit diagram:
- The top gate is a two-input AND gate with inputs $A$ and $B$. Its output is:
$Y_1=A\cdot B$
- The bottom gate is a two-input NAND gate with inputs $B$ and $C$. Its output is:
$Y_2=\overline{B\cdot C}$
- The final output gate is an OR gate that takes $Y_1$ and $Y_2$ as inputs. Thus, the output $y$ is:
$y=Y_1+Y_2=(A\cdot B)+\overline{B\cdot C}$

2. Analyzing Waveforms Interval-by-Interval:
We translate the voltage levels from the input graphs (where 0 V is logic 0 and 5 V is logic 1):

• For interval $t<t_1$:
$A=0$, $B=0$, $C=1$
$y=(0\cdot 0)+\overline{0\cdot 1}=0+1=1$ (5 V)

• For interval $t_1<t<t_2$:
$A=1$, $B=0$, $C=1$
$y=(1\cdot 0)+\overline{0\cdot 1}=0+1=1$ (5 V)

• For interval $t_2<t<t_3$:
$A=0$, $B=1$, $C=0$
$y=(0\cdot 1)+\overline{1\cdot 0}=0+1=1$ (5 V)

• For interval $t_3<t<t_4$:
$A=1$, $B=1$, $C=0$
$y=(1\cdot 1)+\overline{1\cdot 0}=1+1=1$ (5 V)

• For interval $t_4<t<t_5$:
$A=0$, $B=0$, $C=1$
$y=(0\cdot 0)+\overline{0\cdot 1}=0+1=1$ (5 V)

• For interval $t_5<t<t_6$:
$A=1$, $B=0$, $C=1$
$y=(1\cdot 0)+\overline{0\cdot 1}=0+1=1$ (5 V)

• For interval $t>t_6$:
$A=0$, $B=0$, $C=1$
$y=(0\cdot 0)+\overline{0\cdot 1}=0+1=1$ (5 V)

Conclusion:
Since the output is logic 1 (high level, 5 V) during all intervals, the output terminal $y$ remains at a constant potential of 5 V.